Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

ABSTRACT

A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

TECHNICAL FIELD

[0001] The present invention relates to memory devices, and moreparticularly, synchronous dynamic access memory devices.

BACKGROUND OF THE INVENTION

[0002] Conventional dynamic random access memories (DRAMs) perform datatransfer operations in sequence. That is, when a read or write commandis received and an address is made available, the data transferoperation, either read or write, is performed in its entirety beforeanother command is accepted. Consequently, subsequent commands aredelayed by the entire duration of the original data transfer.

[0003] The overall time to perform the original data transfer may besignificant, because data transfers typically involve several steps, andeach step takes time. For example, for a read operation, control logicof the DRAM must decode the command and address, perform precharge andequilibration, connect a row of memory cells to respective digit lines,allow time for sense amplifiers to develop signals; and transfer datafrom the sense amplifiers to an output data bus. Subsequent commandsmust wait until these operations are completed before they are acceptedby the DRAM. Consequently, reading from and writing to the DRAM must besufficiently slow to allow the original data transfer to be completedbefore a subsequent command is provided.

[0004] To reduce the amount of delay imposed in sequential data transferoperations, DRAMs can be “pipelined.” In pipelining, each of theabove-described steps is performed according to a specific timingsequence. For example, when the original data transfer operationprogresses from a first step (e.g., command and address decode) to asecond step (e.g., read data), a second data transfer progresses to itsfirst step (command and address decode). Thus, the DRAM's control logiccan begin decoding the second command and the DRAM's address decoder canbegin decoding the second address while the data from the original datatransfer operation is being read from or written to the memory array.

[0005] To control the flow of data through a pipelined DRAM, commandsand data are transferred synchronously, and such DRAMs are referred toas synchronous DRAMs (“SDRAMs”). In SDRAMs, timing of operations isestablished relative to the leading edges of a clock signal CLK. Atfixed times relative to the leading edges, commands are read by thecontrol logic, addresses are decoded by an address decoder, signals aredeveloped on input and output lines of the memory array, and data ismade available for reading or writing at a data bus.

[0006] In synchronous read operations, an output of data on the data busresults from a read command and an address received at a precedingleading edge of the clock. The delay in number of clock cycles betweenthe arrival of the read command at the control logic input and theavailability of the corresponding data at the data bus is the “latency”of the SDRAM. If the output data is available by the second leading edgeof the clock following the arrival of the read command, the device isdescribed as a two-latency SDRAM. If the data is available at the thirdleading edge of the clock following the arrival of the read command, thedevice is a three-latency SDRAM.

[0007] In conventional SDRAMs, latency is only imposed for readoperations. In write operations, write commands are suppliedsimultaneously with data at the data bus. The commands, addresses, anddata are transferred to the memory array very quickly, typically withinone clock cycle. Typical SDRAMs may thus be described as having no writelatency.

[0008]FIG. 1 is a block diagram of a conventional synchronous dynamicrandom access memory 40 (“SDRAM”). The SDRAM 40 has as its centralmemory element a memory array 42 that is segmented into two banks 44,46. The SDRAM 40 operates under control of a logic controller 48 thatreceives a system clock signal CLK, a clock-enable signal CKE, andseveral command signals that control reading from and writing to theSDRAM 40. Among the command signals are a chip-select signal {overscore(CS)}, a write-enable signal {overscore (WE)}, a column address strobesignal {overscore (CAS)}, and a row address strobe signal {overscore(RAS)}. The overbars for the command signals {overscore (CS)},{overscore (WE)}, {overscore (CAS)} and {overscore (RAS)} indicate thatthese signals are low-true signals, i.e., the command signals {overscore(CS)}, {overscore (WE)}, {overscore (CAS)} and {overscore (RAS)} go to alow logic level when true.

[0009] In addition to the command signals, the SDRAM 40 also receivesaddresses from the address bus 52 and receives or outputs data on a databus 60. The received addresses may be row or column addresses. In eithercase, addresses from the address bus 52 are clocked in the SDRAM 40through an address register or address latch 62. If an address is a rowaddress, the address is transmitted to the array 42 through a rowaddress path 64. The row address path 64 includes a row addressmultiplexer 66 that receives the external row address from the addresslatch 62 and receives an internal row address from a refresh circuit 67.The row address multiplexer 66 provides the row addresses to either oftwo row address latches 70 depending upon the logic state of the bankaddress BA. The row address latches 70 latch the row addresses andprovide the row addresses to respective row decoders 72. The rowdecoders 72 take the 11-bit address from the row address latch 70 andactivate a selected one of 2,048 row address lines 73. The row addresslines 73 are conventional lines for selecting row addresses of locationsin the memory array 42. As noted above, the following discussion assumesthat the row address has been selected and that the selected row isactivated.

[0010] If the address received at the address latch 62 is a columnaddress, it is transmitted to the I/O interface 54 and the memory array42 through a column address path 76. The column address path includes acolumn address counter/latch 78 that receives or increments, and holdsthe column address from the address latch 62, a multiplexer 79 thatreceives a column address from either address latch 62 or fromcounter/latch 78, a pre-decoder 102 and a latch 82. Depending on whethera particular column access is the result of a new command, or if it is asubsequent access in a burst initiated by a previous command, themultiplexer 79 transmits the appropriate column address to the columndecoder 84, via the column address pre-decoder 102 and latch 82. For newcommands, the multiplexer 79 routes the external address (from theaddress latch 62) through to the pre-decoder 102 and latch 82. A copy isalso captured by the column address counter/latch 78 for incrementing onsubsequent accesses. If the device 40 has been programmed for a burstlength of 2 or greater, and a new column command is not presented tointerrupt a column command issued on the previous clock edge, then thecounter/latch 78 will increment (or sequence) to the next column addressin the burst, and the multiplexer 79 will route the incremented addressto the pre-decoder 102 and latch 82.

[0011] The input data path 56 transmits data from the data bus 60 to theI/O interface 54. The output data path 58 transmits data from the I/Ointerface 54 to the data bus 60. Operation of the column address path76, input data path 56, and output data path 58 for a selected sequenceof read and write commands will be described below with respect to thetiming diagram of FIG. 4. The logic controller 48 decodes the commandsignals according to a predetermined protocol to identify read, write,and other commands for execution by the SDRAM 40. FIGS. 2 and 3 showclock and command signals and their states for write commands and readcommands, respectively. The read and write commands differ only in thestate of the write-enable signal {overscore (WE)}. Except for thewrite-enable signal {overscore (WE)}, the following discussion appliesequally to FIGS. 2 and 3.

[0012] As indicated by the arrow 50, the leading edge of each pulse ofthe clock signal CLK establishes the time at which the states of thesignals are determined. The clocking of the logic controller 48 by theclock signal CLK is enabled by the clock-enable signal CKE, which ishigh for reading and writing. Also, reading and writing from the SDRAM40 is enabled only when the SDRAM 40 is selected, as indicated by thechip-select signal {overscore (CS)}.

[0013] The next two command signals are the row and column addressstrobe signals {overscore (RAS)} and {overscore (CAS)}. When true (low),the row address strobe signal {overscore (RAS)} indicates addresses onan address bus 52 are valid row addresses. A true (low) column addressstrobe signal {overscore (CAS)} indicates that addresses on the addressbus 52 are valid column addresses. During reading or writing, the columnaddress strobe signal {overscore (CAS)} is low (true) indicating thatthe address bits from the address bus 52 represent the column address,as represented for address signals A0-A10. The row address strobe signal{overscore (RAS)} is high (not true) because the row address wasdetermined at a different leading clock edge. As is conventional toSDRAM operation, the row address is received and stored and the selectedrow is activated prior to the column address strobe signal {overscore(CAS)} going true (low). The following discussion assumes that theselected row has already been activated.

[0014] The write-enable signal {overscore (WE)} becomes active at thesame time that the column-address strobe signal {overscore (CAS)}becomes active. The write-enable signal {overscore (WE)} is also alow-true signal such that, if the write-enable signal {overscore (WE)}is low, the data transfer operation will be a write, as shown in FIG. 2.If the write-enable signal {overscore (WE)} is high, the data transferoperation will be a read, as shown in FIG. 3.

[0015] The logic controller 48 decodes the above-described commandsignals CKE, CLK, {overscore (CS)}, {overscore (WE)}, {overscore (CAS)},and {overscore (RAS)} to determine whether a read or write command hasbeen received. In response to the determined command, the logiccontroller 48 controls reading from or writing to the memory array 42 bycontrolling an I/O interface 54 and input and output data paths 56, 58.The I/O interface 54 is any conventional I/O interface known in the art,and includes typical I/O interface elements, such as sense amplifiers,mask logic, precharge and equilibration circuitry, and input and outputgating.

[0016] The following discussion of FIG. 4 assumes that the row addresshas already been decoded and the appropriate row of the memory array 42has been activated in response to the row address. As shown in FIG. 4, afirst read command READ1 is applied to the logic controller 48 at aleading edge of a first clock pulse at time to. At substantially thesame time, a first read column address RCOL1 is applied to the addressbus 52. Over the next two periods of the clock signal CLK, the firstread column address RCOL1 travels along the column address path 76through the address latch 62, the multiplexer 79, the column addresspredecoder 102 and latch 82 to the column decoder 84 where it isdecoded. The decoded read column address RCOL1 reaches the I/O interface54 by time t2, at the second leading edge following the time t0.

[0017] Upon the decoded column address RCOL1 reaching the array 42, theI/O interface 54 reads data DOUT1 stored in the memory location at thedecoded column address RCOL1 and provides the data DOUT1 to the outputdata path 58. The data DOUT1 travel through the output data path 58 andreaches the data bus 60 at time t3, which is three leading edges of theclock signal CLK after the first read command READ1 was received at timet0. The SDRAM 40 is thus a three-latency device because the data DOUT1are available at the data bus 60 three leading edges of the clock signalCLK after the read command READ1 arrives at time t0.

[0018] A subsequent read command READ2 and a second column address RCOL2arrive at time t1, which is the leading edge of the clock signal CLKimmediately after the first leading clock edge at time t0. Theabove-described reading operations occur in response to the second readcommand READ2 and the second column address RCOL2, with each stepshifted to the right by one period of the clock signal CLK relative tothe operations of the first read command RCOL1. The data DOUT2 from thesecond memory location indicated by the column address RCOL2 are appliedto the data bus 60 at time t4.

[0019] At time t2, a third read command READ3 and third column addressRCOL2 are applied to the logic controller 48 and address bus 52,respectively. Once again, the read operations are repeated, one clockperiod after those of the second read operation. Thus, the data DOUT3for the third read command READ3 are applied to the output data bus 60at time t5.

[0020] While read operations are performed according to the read latencyof the SDRAM 40, there is typically no write latency in the DRAM 40.However, the read latency of the SDRAM 40 can delay the completion ofwrite operations that follow a read operation. FIG. 4 shows an exampleof an attempt to write data at time t3 immediately following the thirdread command READ3 at time t2. The write command WRITE1, the columnaddress WCOL1, and the input data DIN1 are all applied to the logiccontroller 48, the address bus 52, and the data bus 60, respectively, attime t3. The decoded column address WCOL1 and input data DIN1 arrive atthe array 42 approximately one clock cycle later. In the example of FIG.4, the address WCOL1 and data DIN1 take approximately one clock cycle totraverse the column address path 76 and the input data path 56,respectively. However, in some SDRAMs, the data DIN1 and the decodedcolumn address WCOL1 may arrive at the array 42 more quickly or moreslowly.

[0021] One problem with the above-described timing structure is that attime t3, the input data DIN1 from the first write command WRITE1 and theoutput data DOUT1 from the first read command READ1 would collide at thedata bus 60.

[0022] A second data collision occurs when a second write command WRITE2immediately follows the first write command WRITE1. More specifically,at time t4, input data DIN2 for the second write command WRITE2 reachesthe data bus 60 at the same time that output data DOUT2 from the secondread command READ2 reach the data bus 60. A third data collision occurswhen a third write command WRITE3 immediately follows the second writecommand WRITE2. This occurs at time t5 when input data DIN3 from thethird write command WRITE3 and output data DOUT3 reach the data bus 60simultaneously.

[0023] To prevent such data collisions, most SDRAMs require that writecommands be delayed with respect to the read commands so that writecommands are not permitted for one or more clock cycles after readcommands. Typically, this is achieved by inserting no operation commandsNO-OP between read and write commands. While this approach can preventsuch collisions, the no operation commands NO-OP lower the effectivespeed of such SDRAMs because they impose delays in accepting writecommands at the SDRAM. Note that this problem does not occur for readcommands following write commands since the write command can beprocessed during the read latency period.

[0024] Another approach to preventing such data collisions might be toimpose write latencies that equal the read latencies. As used herein, a“write latency” refers to the number of clock cycles between a writecommand and arrival of data on the data bus 60. Such an approachinherently avoids collisions of data and addresses on a computer's databus and address bus because data and addresses will follow read andwrite commands by equal numbers of clock cycles. Thus, as long as thecommands are not issued simultaneously, data and addresses will notcollide on the data and address busses. One example of such an approachis found in U.S. Pat. No. 5,511,024 to Ware et al.

[0025] Unfortunately, this approach does not necessarily overcome theproblems of data collisions and address collisions at the memory array42, as can be seen in FIG. 5. As shown at time t3, a first write commandWRITE1 and a first write column address WCOL1 are applied to the SDRAM40. At time t4 a second write command WRITE2 and second write columnaddress WCOL2 are applied. Input data DIN2 corresponding to the secondwrite command WRITE2 are present on the data bus (DQ) at time t7,assuming a write latency of three. One leading edge later, at time t8,the input data DIN2 and the decoded second column address WCOL2 reachthe array 42, assuming the second write address WCOL1 is internallydelayed (buffered) and applied to the array 42 at the appropriate time.

[0026] At time t6, a fourth read command READ4 and fourth read addressRCOL4 are applied to the logic controller 48 and the address bus 52,respectively. The decoded column address RCOL4 reaches the array at timet8 and the data DOUT4 is read from the array at time t8. However, as canbe seen in FIG. 5, the decoded column addresses WCOL2 and RCOL4 bothreach the array 42 at time t8. Also, the input data DIN2 and output dataDOUT4 are being written to and read from the array 42 at time t8. Thus,reading and writing with the same latency might still result in data andaddress collisions at the array 42. One approach to overcoming thislimitation could be to limit reads and writes to separate DRAMs or toseparate independent arrays of a multi-array device. This approach stillprecludes sequential reads and writes at matching latencies within asingle memory array. Also, a multi-bank memory array approach wouldrequire multiple independent memory arrays and associated columnamplifiers to interleave reads from one bank with writes to anotherbank.

SUMMARY OF THE INVENTION

[0027] A synchronous dynamic random access memory (“SDRAM”) isconfigured to perform both read and write operations with the samelatency while avoiding data and address collisions internal to thedevice. In one embodiment of the invention, the SDRAM includes interimaddress registers in a column address path and interim data registers inan input data path. In response to a write command, corresponding writeaddress and corresponding input data the SDRAM stores the write addressin one of the interim address registers and stores the input data in oneof the interim data registers.

[0028] A logic controller within the SDRAM monitors subsequent commandsto determine an available write interval at a memory array in the SDRAM.When the logic controller identifies an upcoming available writeinterval, the logic controller initiates transfer of the stored addressfrom the interim address register and stored input data from the interimdata register to an I/O interface. There, the input data is written tothe location corresponding to the address.

[0029] The address path includes N+1 registers where N is the latency ofthe device, so that more than one address can be stored in the interimaddress registers. Additionally, the input data path includes N interimdata registers to store the corresponding input data.

[0030] In one embodiment of the invention, the SDRAM also includes abypass path between the input data path and an output data path.Additionally, the column address path includes an address predecoder anda comparator that compare incoming read addresses with stored addressesin the interim address registers. If the comparator determines that anincoming read address matches a stored write address in one of theinterim address registers, the comparator activates a multiplexer in theinput data path to transfer data from the corresponding interim dataregister to the output path. The data from the interim data register isthus provided at an output data bus in place of data from the array.Thus, this embodiment prevents reading from addresses in which data hasnot yet been updated.

[0031] A computer system according to the invention includes a memorycontroller that controls the SDRAM. With the embodiment described above,the controller need not keep track of buffered addresses for the purposeof avoiding reads to that data. In another embodiment, the memorycontroller includes interim address and data registers and a comparatorto prevent reading of data from address locations that have not yet beenupdated. In another embodiment, the memory controller identifiesattempts to read from addresses that have not yet been updated andinserts no operation commands to allow the data to be written to thearray before the read operation is performed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a block diagram of a conventional synchronous dynamicrandom access memory (“SDRAM”).

[0033]FIG. 2 is a signal timing diagram showing states of variouscommands signals forming a write command.

[0034]FIG. 3 is a signal timing diagram showing states of variouscommand signals forming a read command.

[0035]FIG. 4 is a timing diagram of signals for read and writeoperations within a conventional synchronous dynamic random accessmemory showing data and address collisions at the memory array and atthe data bus.

[0036]FIG. 5 is a signal timing diagram of four latency read and fourlatency write operations in a hypothetical SDRAM according to FIG. 1,showing data and address collisions at the memory array.

[0037]FIG. 6 is a block diagram of an SDRAM according to one embodimentof the invention, including interim address and interim data registersin a column address path and a data input path, respectively.

[0038]FIG. 7 is a signal timing diagram of signals for four latency readand four latency write operations in the SDRAM of FIGS. 6 and 9.

[0039]FIG. 8 is a block diagram of an SDRAM according to anotherembodiment of the invention, including interim address registers andinterim data registers and an array bypass for reading data posted inthe interim data registers.

[0040]FIG. 9 is a block diagram of a computer system including the SDRAMof FIGS. 6 or 9, including a memory controller, microprocessor, displaydevice and input and output devices.

DETAILED DESCRIPTION OF THE INVENTION

[0041] As shown in FIG. 6, an SDRAM 100 according to one embodiment ofthe invention operates with equal read and write latencies whileavoiding collision at the memory array 42. The SDRAM 100 includes manyelements that are identical to or analogous to elements of FIG. 2, whereidentical or analogous elements are numbered the same. Unlike the SDRAM40 of FIG. 4, the SDRAM 100 of FIG. 6 includes column interim addressregisters 104 and an auxiliary address multiplexer 106 in the columnaddress path 76. Also unlike the SDRAM 40 of FIG. 4, the SDRAM 100 ofFIG. 6 includes interim data registers 108 and an input data multiplexer110 in the input data path 56. Further differences in the SDRAM 100 arefound in the timing of operations established by the logic controller48. These timing differences will become apparent as operation of theSDRAM 100 of FIG. 6 is described with reference to the signal timingdiagram of FIG. 7.

[0042] The SDRAM 100 of FIG. 6 performs both read and write operationswith latencies of three. However, unlike the embodiment of FIG. 5, theSDRAM 100 of FIG. 6 avoids data and address collisions by temporarilystoring data and addresses in the interim address and data registers104, 108.

[0043] As seen in FIG. 7, the SDRAM 100 operates according to the sameclock signal CLK, read and write commands and input data described abovewith reference to FIGS. 1-3 and 5. The timing diagram of FIG. 7 showssignals and commands for a series of three read commands followed bythree write commands, followed by three read commands. One skilled inthe art will recognize that several other series of commands can beapplied. However, the series of FIG. 7 shows how the SDRAM 100 of FIG. 6avoids data and address collisions for any series of commands withoutrequiring no operation commands.

[0044] As shown in the first diagram of FIG. 7, at time t0, a first readcommand READ1 and first read column address RCOL1 are applied to thelogic controller 48 and address bus 52, respectively. The read columnaddress RCOL1 passes through the address latch 62 by time t1 and thenthrough the multiplexer 79. The read column address RCOL1 is thenapplied to the address predecoder 102. The address predecoder 102decodes the first read column address RCOL1 and stores the predecodedaddress RCOL1 in a first of the interim address registers 104 by timet2. Before time t2, the first read column address RCOL1 becomesavailable at the output of the interim register 104 and is clockedthrough the auxiliary address multiplexer 106 and into the columndecoder 84. The column decoder 84 decodes the read column address RCOL1and provides a pulse to the selected column of the array 42 as indicatedby the decoded column signal COL-DEC. The pulse of the decoded columnsignal COL-DEC arrives at the selected array column before time t2. Inresponse to the decoded read column address RCOL1 (including the pulseof the decoded column signal COL-DEC) and the read command, the I/Ointerface 54 reads output data DOUT1 from the location indicated by theaddress RCOL1, as indicated by the signal line INTERNAL I/O DATA in FIG.7. The output data DOUT1 arrive at a read data latch 105 at about timet2. The data DOUT1 then pass through the remainder of data output path58 and reach the output data bus 60 by time t3, which is three clockedges following the first read command READ1.

[0045] A second read command READ2 and second read column address RCOL2are applied to the SDRAM 100 at time t1, which is one clock cyclefollowing the first read command READ1. The second read column addressRCOL2 follows the same path as the first read column address RCOL1,except that the second read column address RCOL2 reaches each locationin the column address path 76 one clock cycle later. The output dataDOUT2 are thus available at the data bus 60 at time t4.

[0046] A third read command READ3 and a third column address RCOL3 arepresent at time t2, and the read process is repeated as described above.The corresponding output data DOUT3 reach the data bus 60 at time t5.

[0047] At time t3, a first write command WRITE1 and a first write columnaddress WCOL1 are applied to the logic controller 48 and the address bus52, respectively. The corresponding input data DIN1 arrive three clockedges later, at time t6, in order to match the read latency. The writecolumn address WCOL1 passes along the column address path 76 through thecolumn address counter/latch 78, multiplexer 79, and column addresspredecoder 102, as described above, and reaches the interim addressbuffers 104 at time t4. The write column address WCOL1 is loaded intothe uppermost interim address register 104 as indicated at the signalline REG1.

[0048] Unlike the read column addresses RCOL1, RCOL2, RCOL3, the firstwrite column address WCOL1 does not transfer quickly through the interimaddress register 104 to the auxiliary address multiplexer 106 and columnaddress buffer 82 to the column decoder 84. Instead, the write columnaddress WCOL1 remains in the uppermost interim address register 104 fora substantial period of time. In fact, the write column address WCOL1remains in the uppermost interim address register 104 until the logiccontroller 48 determines that the corresponding input data DIN1 can bewritten to the array 42 without an address collision. Similarly, theinput data DIN1 is stored in the uppermost interim data register 108until it can be written to the array 42 without a data collision. Theinterval when input data can be written to the array 42 without anaddress or data collision will be referred to herein as an “availablewrite interval.”

[0049] To determine when an available write interval occurs and thusavoid data and address collisions, the logic controller 48 “looks ahead”to determine the usage of the array 42 in view of the latency of theSDRAM 100 and the commands and data following the first write commandWRITE1. The determination of an available write interval can be seen byconsidering the time when the input data DIN1 can be written to thearray.

[0050] First, the input data DIN1 corresponding to the write commandWRITE1 do not reach the data bus 60 until time t6, because the writeoperation is a three-latency operation. Thus, the input data DIN1 cannotbe written to the memory array 42 until after time t6. Consequently, thefirst write column address WCOL1 will not be transferred from theinterim address register 104 to the I/O interface 54 until at least timet6, which is the clock edge on which the input data DIN1 reach the databus 60.

[0051] Even though the input data DIN1 are available at time t6, thelogic controller 48 still does not initiate transfer of the write columnaddress WCOL1 at time t6. This is because the third command followingthe write command WRITE1 is a read command READ4 at time t6. The readcommand READ4 at time t6 means that the decoded read address RCOL4 willreach the I/O interface 54 two clock cycles later at time t8, at whichtime the output data DOUT4 will occupy the I/O interface 54 and array42. To ensure that the decoded read command READ4 will arrive at the I/Ointerface 54 at time t8, the read column address RCOL4 exits thelowermost interim address register 104 between times t7 and t8. Thus, ifthe logic controller 48 were to transfer the write column address WCOL1at time t7, both the write column address WCOL1 and the read columnaddress RCOL4 would collide at the I/O interface 54 at time t8.Similarly, the input data DIN1 take at least one clock cycle to passfrom the data bus 60 through the input data path 56 to the I/O interface54. Thus, the input data DIN1 and the output data DOUT4 could alsocollide at the I/O interface 54.

[0052] The logic controller 48 also does not initiate transfer of thewrite column address WCOL1 at time t8 because a fifth read command READ5arrives at time t7. The fifth read column address RCOL5 from the fifthread command READ5 applied at time t7 would thus occupy the I/Ointerface 54 and array 42 at or slightly before time t9. Consequently,the fifth read column address RCOL5 and the first write column addressWCOL1 could collide at time t9 if the logic controller 48 initiatedtransfer of the input data DIN1 from the interim address register 104 attime t8. Also, the input data DIN1 and the output data DOUT5 couldcollide at time t9 under these conditions.

[0053] Likewise, the logic controller 48 does not initiate transfer ofthe write column address WCOL1 from the interim address register 104 attime t9, because of the address collision that could occur at time t10between the first write column address WCOL1 and the sixth read columnaddress RCOL6 from the sixth read command READ6 and because of the datacollision that would occur between the input data DIN1 and the outputdata DOUT6.

[0054] As can be seen from the above discussion, the write columnaddress WCOL1 remains in the interim address register 104 as long asread commands continue to be applied. However, once a write command (orany other command that will produce an opening at the I/O interface 56,such as a no operation NO-OP command) arrives, the logic controller 48can predict that the memory array 42 will soon be available for writing(in two clock cycles).

[0055] At time t9, the fourth write command WRITE4 is applied to thelogic controller 48. The fourth write command WRITE4 will not occupy theI/O interface 54 at time t11 because writes are three latency and theassociated data DIN4 is not available yet. Consequently, the logiccontroller 48 determines that time t11 is an available write interval.Accordingly, at time t10, the logic controller 48 initiates transfer ofthe write column address WCOL1 from the uppermost interim addressregister 104 through the multiplexer 106 and column decoder 84 to theI/O interface 54. The write column address WCOL1 thus arrives alone atthe I/O interface 54 at time t11.

[0056] The SDRAM 100 prevents data collisions at the I/O interface 54 ina similar fashion by holding the input data DIN1 in the uppermostinterim data register 108 until time t10, which is one clock cyclebefore the available write interval of time t11. At time t10, the logiccontroller 48 initiates transfer of the input data DIN1 through theinput data multiplexer 110 to the I/O interface 54, such that the inputdata DIN1 arrive at the I/O interface 54 at time t11. The I/O interface54 writes to the array 42 at time t11, because both the first writecolumn address WCOL1 and the corresponding input data DIN1 are present.

[0057] As can be seen from FIG. 7, a second write command WRITE2 and asecond write column address WCOL2 reach the SDRAM 100 at time t4. Thecorresponding input data DIN2 arrive three leading edges later at timet7. As with the first write column address WCOL1, the second writecolumn address WCOL2 passes through the column address path 76 to theinterim address registers 104. When the second write column addressWCOL2 arrives at the interim address registers 104, the uppermostinterim address register 104 is already occupied by the first writecolumn address WCOL1. Therefore, the second write column address WCOL2,is placed in the second interim address register 104 until a secondavailable interval arrives at time t12.

[0058] In a similar fashion, the second input data DIN2 reach the dataaddress bus 60 at time t7 and enter the second interim data register108, because the first interim data register 108 is already occupiedwith the first input data DIN1. At time t11, the second input data DIN2are transferred from the second interim data register 108, and reach theI/O interface 54 at the second available write interval at time t12.Thus, both the second write column address WCOL2 and the second inputdata DIN2 are available at the I/O interface 54 at time t12 and thesecond input data DIN2 are written to the array 42.

[0059] The above-described procedure is once again repeated for a thirdwrite command WRITE3 and third write column address WCOL3 that arrive attime t5 and their corresponding input data DIN3 that arrive at time t8.The third write column address WCOL3 occupies the third interim addressregister 104 and the third input data DIN3 occupy the third interim dataregister 108 until time t12 when they transfer to the I/O interface 54.

[0060] A fourth read command READ4 and fourth read column address RCOL4reach the SDRAM 100 at time t6. As described above, the read columnaddress RCOL4 passes through the column address path 76 to the interimaddress registers 104. The read column address RCOL4 passes directlythrough the fourth interim address register 104, and continues throughthe multiplexer 106 and the column decoder 84 directly to the I/Ointerface 54. The fourth read column address RCOL4 can pass undelayedbecause the first, second, and third write column address commandsWCOL1, WCOL2, and WCOL3 are held in the first three interim addressregisters 104 until the read column address RCOL4 has left the I/Ointerface 54. The output data DOUT4 can pass through the I/O interface54 to the output data path 58 at time t8 because the input data DIN1,DIN2, and DIN3 are held at the interim data registers 108 until afterthe output data DOUT4 pass through the output data path 58.

[0061] At time t7, a fifth read command READ5 reaches the SDRAM 100, andthe above-described procedure is repeated such that the output dataDOUT5 is available at time t10.

[0062] As described above, the SDRAM 100 can perform both reads andwrites with three latency by temporarily storing the write columnaddresses and input data in the interim address and data registers 104,108, thereby preventing data and/or address collisions at the I/Ointerface 54. One skilled in the art will recognize that the SDRAIM 100can perform subsequent reads and writes using N+1 interim addressregisters 104 where N is the latency of the SDRAM 100, regardless of thenumber of read commands that follow a write command and regardless ofthe number of write commands performed in sequence. Additionally, theSDRAM 100 can perform such sequential read and write operations using(N) interim data registers 108.

[0063]FIG. 8 shows another embodiment of the SDRAM 100 that addressesthe situation where a read command is directed toward an address that iscurrently being held in one of the interim address register 104. Thissituation may occur if, for example, the fourth read column addressRCOL4 is the same address as the first write column address WCOL1. Inthis situation, the output data DOUT4 for the fourth read command READ4should be the input data DIN1 from the first write command WRITE1.However, the array 42 would not yet contain the proper input data (inputdata DIN1), because the input data DIN1 has not yet been written to thearray 42 from the first interim data register 108. Consequently, theSDRAM 100 could provide the incorrect data at the output data bus 60 inresponse to the fourth read command READ4.

[0064] The SDRAM 120 of FIG. 8 treats such situations internally byadding an address comparator 122 coupled to the interim addressregisters 104 and the predecoder 121. Additionally, the SDRAM 120includes an output data multiplexer 124 in the output data path 58 thatreceives output data from the I/O interface 54 and that can receiveinput data from the interim data registers 108 through the input datamultiplexer 110 via a bypass path 126.

[0065] Operation of the SDRAM 120 of FIG. 8, under normal conditions, issubstantially the same as operation of the SDRAM 100 of FIG. 6. However,in the SDRAM 120, as each new address is output by the predecoder 121,the address comparator 122 compares the addresses in each of the interimcolumn address registers 104 to the newly applied address. If theaddress comparator 122 detects that the arriving address is a readcolumn address RCOL* that matches a write column address WCOL* in one ofthe interim address registers 104, the address comparator 122 producescontrol signals on control lines 128, 131, to control the input datamultiplexer 110 and output data multiplexer 124. In response to thecontrol signals, the multiplexers 110 provide the input data DIN*corresponding to the matching write column address WCOL* from thecorresponding interim data register 108 to the bypass path 126. Theoutput data multiplexer 124 supplies the re-routed input data DIN* fromthe bypass path 126 to an output data register 129, in place of theoutput data DOUT* from the I/O interface 54. The input data DIN* thusarrive at the data bus 60, rather than data read from the location inthe array 42 corresponding to the matching read address RCOL*. Thus, theimproper data from the array 42 are blocked from reaching the outputdata bus 60 and the proper data DIN* and reach the data bus 60 throughthe bypass path 126. Even though the input data DIN* follow the bypasspath 126 to the data bus 60, the input data DIN* are still provided tothe memory array 42 at the appropriate available write interval so thatthe incorrect data in the memory array 42 is replaced by the correctdata DIN*.

[0066] The problem of such an incorrect data read may not be critical inall situations, because some applications may operate adequately withoccasional data errors. One example of a possible noncritical error isin a two-dimensional video display application where a video imageincludes many thousands of pixels. If a very few of the data bits areincorrect, the effect on the overall image would be negligible. In fact,the number of bit errors will be low because the above-describedread-following-write operations to common addresses are rare. Thus, theembodiment of FIG. 6 may be preferred in some applications because ofits simplicity and speed. In other applications, where data integrity isimportant, such as accounting programs, the embodiment of FIG. 8 wouldbe preferred. Alternatively, as discussed below, the embodiment of FIG.6 may be used in applications requiring data integrity, by programmingthe logic controller 48 to block reading of data from not-yet-writtenaddresses.

[0067] Also, in some applications, such as certain packetized systems ordata networks, it may be desirable to select data from the memory array42 rather than from the interim data registers 108 when the storedaddress matches an address in the interim address register 104. Forexample, such a capability may allow retrieval of a lost data packet ina packetized system. The logic controller 48 can implement suchcapability in the SDRAM 100 by selectively enabling or disabling thecomparator 122 responsive to external commands or to a preprogrammedalgorithm. Although the preferred embodiment of the invention avoidsdata collisions by temporarily storing the write data and writeaddresses while a read operation is processed, alternative techniquesmay be used. For example, a data collision resulting from a writefollowed by a read may be avoided by temporarily storing the readaddress in a temporary address buffer until the write data has beenstored in the array. The read address is then transferred from temporaryaddress buffer to the array for the read operation.

[0068]FIG. 9 is a block diagram of a computer system 130 that includesthe SDRAM 100 and a memory controller 136. The computer system 130includes computer circuitry 132 for performing such computer functionsas executing software to perform desired calculations and tasks. Thecomputer circuitry 132 typically contains a processor 134, the memorycontroller 136 and the SDRAM 100 as shown. One or more input devices144, such as a keyboard or a pointing device, are coupled to thecomputer circuitry 132 and allow an operator (not shown) to manuallyinput data thereto. One or more output devices 146 are coupled to thecomputer circuitry 132 to provide data generated by the circuitry to theoperator. Examples of output devices 146 include a printer and a videodisplay unit. One or more data storage devices 148 are coupled to thecomputer circuitry 132 to store data in or retrieve data from externalstorage media (not shown). Examples of storage devices 148 andassociated storage media include drives that accept hard and floppydisks, magnetic tape recorders, and compact-disc read only memory(CD-ROM) readers.

[0069] The memory controller 136 provides an alternative structure foravoiding the above-described read-following-write to a common locationfor use with the SDRAM 100. To avoid such situations, the alternativememory controller 136 includes interim address and data registers 138,140 and a comparator circuit 142 that temporarily store data andaddresses and compare incoming read addresses to write addresses in theinterim address registers 138 in the fashion described above withrespect to FIG. 8.

[0070] If the comparator 142 does not indicate a match (i.e., an attemptto read data from an address that is not yet written), addresses anddata are forwarded, in the order received, to the SDRAM 100 throughmultiplexers 139, 141. If the comparator 142 indicates a match (i.e., anattempt to read from a location that is not yet written), the comparator142 activates multiplexers 141, 143 to direct data from the interim dataregisters 140 along a bypass path 145 to the output device 146 or theprocessor 134. As described above, the correct data are outputimmediately and are written later to the SDRAM 100 at an available writeinterval. Alternatively, the memory controller 132 may insert nooperation NO-OP steps to delay the read command until after the writeoperation is completed.

[0071] While the present invention has been explained by way ofexemplary embodiments, various modifications may be made withoutdeparting from the spirit and scope of the invention. For example, thecomputer system 130 of FIG. 9 can use the SDRAM 120 of FIG. 8 andthereby eliminate the interim address, data registers 138, 140,multiplexers 139, 141, 143, and comparator circuit 142. Also, the SDRAMs100, 120 have been described as three-latency devices. However, thestructures and methods described herein can be applied to SDRAMs havingany latency. Also, the structures and methods described herein can alsobe applied to a variety of other synchronous devices, such as packet orprotocol-type synchronous memory devices. Moreover, although thedescription of the exemplary embodiments herein describes application toa single memory array 42, one skilled in the art will recognize that theprinciples described herein are equally applicable to avoidingcollisions, at subarrays or banks, and that references to the memoryarray 42 could also refer to memory subarrays or banks. Many otherdevices could be developed that operate the same way and would be withinthe scope of the invention. Accordingly, the invention is not limitedexcept as by the appended claims.

1. An integrated memory device having a read or write latency of N whereN is a real number greater than 1, comprising: a memory array; a commandinput terminal; a data bus; address input terminals; an output data pathcoupled to the memory array; a control circuit coupled to the commandinput terminal and responsive to a predetermined sequence of commandsignals at the command input terminal to produce a control signalindicative of either an anticipated data collision or an available reador write interval at the memory array; and an address path between theaddress input terminals and the memory array, the address path includingan at least one interim address register, each of the interim addressregisters being configured to store a respective input address, each ofthe interim address registers being operative to retain the storedaddress in response to the control signal indicative of the anticipateddata collision or to apply the address to the array in response to thecontrol signal indicative of the available read or write interval at thememory array.
 2. The memory device of claim 1, further comprising: aninput data path including at least N−1 interim data registers coupledbetween the data bus and the memory array, each of the interim dataregisters being configured to store a respective set of write data, eachof the interim data registers being operative to retain the stored datain response to the control signal indicative of the anticipated datacollision or to transfer the stored data to the memory array in responseto the control signal indicative of the available read or writeinterval.
 3. The memory device of claim 1, further comprising: acomparing circuit coupled to receive incoming addresses before theincoming addresses are applied to the array, the comparing circuitfurther being coupled to the interim address register, the comparingcircuit being operative to produce a compare signal in response to anincoming address matching a stored previously received address from theinterim address register.
 4. An integrated memory device having a readlatency of N where N is a real number greater than 1, comprising: amemory array; a command input terminal; a data bus; an output data pathcoupled to the memory array; a control circuit coupled to the commandinput terminal and responsive to a predetermined sequence of commandsignals at the command input terminal to produce a control signalindicative of an anticipated data collision or an available writeinterval at the memory array; and an input data path including at leastN−1 interim data registers coupled between the data bus and the memoryarray, each of the interim data registers being configured to store arespective set of write data, each of the interim data registers beingoperative to retain the stored data in response to the control signalindicative of the anticipated data collision or to transfer the storeddata to the memory array in response to the control signal indicative ofthe available write interval.
 5. The memory device of claim 4, furthercomprising: address input terminals; an address path between the addressinput terminals and the memory array, the address path including aninterim address register; and a comparing circuit coupled to receiveincoming addresses before the incoming addresses are applied to thearray, the comparing circuit further being coupled to the interimaddress register, the comparing circuit being operative to produce acompare signal in response to an incoming address matching a storedpreviously received address from the interim address register.
 6. Thememory device of claim 5, further comprising a bypass path from theinterim data registers to the output data path, the bypass path beingresponsive to provide data from the interim data register to the outputdata path in response to the compare signal.
 7. The memory device ofclaim 4 wherein the output data path includes serially coupled first andsecond output data registers coupled to receive data from the memoryarray.
 8. The memory device of claim 4 wherein the address path furtherincludes an address multiplexer coupled between the interim addressregister and the memory array.
 9. An integrated synchronous memorydevice having a read latency and write latency of N, where N is apositive real number, the memory device being operative to accept a readcommand within a latency period following a write command, comprising: amemory array, an address input terminal; an address path between theaddress input terminal and the memory array, the address path includingan interim address register operable to store an address correspondingto the write command; an input data path, including an interim dataregister coupled to the memory array, the interim data register beingoperable to store a set of write data corresponding to the writecommand; and a look-ahead circuit configured to detect an upcomingavailable write interval at the memory array following the read command,the look-ahead circuit being configured to activate the interim dataregister and the interim address register in response to the detectedupcoming available write interval, to provide the stored write addressfrom the interim address register and the stored set of write data fromthe interim data register to the memory array.
 10. The memory device ofclaim 9, further comprising a comparing circuit coupled to receiveincoming read addresses, the comparing circuit further being coupled tothe interim address register, the comparing circuit being operative toproduce a control signal in response to an incoming read addressmatching the stored write address in the interim address register. 11.The memory device of claim 10, further comprising a bypass path from theinterim data register to the output data path, the bypass path beingresponsive to provide data from the interim data register to the outputdata path in response to the control signal.
 12. The memory device ofclaim 11, further including a multiplexer coupled between the interimdata register and the output data path, the multiplexer further beingcoupled to receive the control signal from the comparing circuit. 13.The memory device of claim 9, further including at least N−2 additionalinterim address register locations such that the number of interimaddress registers is at least N−1.
 14. A computer system, comprising: adisplay; an input device; a timing control circuit; and a synchronousmemory device having a latency of N, where N is greater than 1, thememory device including: a memory array; a command input terminal; adata bus; an input data path; at least N−1 interim data registers in theinput data path, each of the interim data registers coupled to the databus and operable to store a respective set of write data from the databus, the interim data buffers being coupled to the memory array andoperable to transfer the write data to the memory array; an output datapath coupled to the memory array; and a logic controller coupled to thecommand input terminal and operative to predict a collision of thememory array in response to a command sequence at the command inputterminal, the logic controller being configured to block the interimregisters from transferring the write data to the memory array inresponse to the predicted collision.
 15. The computer system of claim14, further comprising: an address input; and an interim addressregister coupled between the address input and the memory array, theinterim address register being operable to store a write address andtransfer the stored write address to the memory array, wherein the logiccontroller is operative to block the transfer of the stored writeaddress to the memory array in response to the predicted collision. 16.The computer system of claim 15, further comprising a comparing circuitcoupled to the address input and the interim address register, thecomparing circuit being operative to produce a control signal inresponse to an incoming read address from the address input matching anaddress in the interim address register.
 17. The computer system ofclaim 16 wherein the comparing circuit is within the synchronous memorydevice.
 18. The computer system of claim 16, further comprising a bypasspath from the interim data registers to the output data path, the bypasspath being responsive to provide data from the interim data register tothe output data path in response to the control signal.
 19. The computersystem of claim 16, further including a memory controller external tothe synchronous memory device, wherein the comparing circuit is in thememory controller.
 20. The computer system of claim 16, furthercomprising an address multiplexer coupled between the interim addressregister and the memory array.
 21. The computer system of claim 15wherein the number of interim address registers is at least N−1.
 22. Anintegrated synchronous memory device having a read latency and a writelatency wherein the read latency and write latency are equal,comprising: a memory array; an address bus configured to receive readand write addresses; an address path coupled between the address bus andthe memory array including an address comparator, the address comparatorbeing operative to provide a control signal in response to a receivedread address matching a write address received at the address bus andstill in the address path; a data bus; an input data path coupledbetween the data bus and the memory array; an output data path coupledbetween the data bus and the memory array; and a bypass circuit coupledbetween the input data path and the output data path, and responsive tothe control signal from the address comparator to provide a bypass pathbetween the input and output data paths.
 23. The memory device of claim22, further comprising: a plurality of interim address registers in theinput address path; and a plurality of interim data registers in theinput data path.
 24. The memory device of claim 23, further comprisingan address multiplexer coupled to outputs of the interim addressregisters.
 25. The memory device of claim 23, further comprising aninput data multiplexer coupled to outputs of the interim data registers.26. The memory device of claim 25 wherein the bypass circuit includes anoutput data multiplexer having an input coupled to the input datamultiplexer.
 27. A method of synchronously reading data from and writingdata to a selected memory array within an integrated memory device,comprising the steps of: providing a first read command during a firstinterval; waiting a selected latency period after the first interval;transferring data from the selected memory array to an output data busby the end of the latency period in response to the first read command;providing a write command at a second interval immediately following thefirst interval and before the end of the latency period; and writingdata to the selected memory array.
 28. The method of claim 27 whereinthe step of writing to the selected memory array comprises the steps of:storing write addresses in an interim address register; storing writedata in an interim data register; detecting an available write intervalat the memory array; retrieving the stored write addresses and storedwrite data from the interim address and data registers in response tothe detected available write interval; and writing the retrieved data toa location in the memory array identified by the retrieved writeaddress.
 29. The method of claim 28 wherein the step of transferringdata from the selected memory array to an output data bus furthercomprises the steps of: comparing a read address to addresses in theinterim address register; if the read address matches one of theaddresses in the interim address register, transferring data from theinterim data register to the output data path; and if the read addressdoes not match one of the addresses in the interim address register,transferring data from the selected memory array to the output datapath.
 30. The method of claim 27, further comprising the steps of:providing a second read command at a third interval immediatelyfollowing the second interval and before the end of the latency period;and reading data from the selected memory array in response to thesecond read command.
 31. A method of synchronously reading and writingdata in a memory device having a memory array according to a clocksignal defining a series of operational intervals, comprising the stepsof: providing a read command during a first operational interval;providing a write command at a second operational interval immediatelyfollowing the first operational interval; in response to the readcommand, completing a read operation at an Nth operational intervalfollowing the first operational interval by N−1 operational intervals,where the N is greater than or equal to 2; and in response to the writecommand, completing a write operation after performing the readoperation.
 32. The method of claim 31 wherein the step of completing awrite operation includes the steps of: accepting a write address;temporarily storing the write address; accepting input data; temporarilystoring the input data; detecting an available interval of the memoryarray; and writing the input data to the memory array at the detectedavailable interval.
 33. The method of claim 32 wherein the step ofcompleting a read operation includes the steps of: comparing a readaddress of the read operation to a set of write addresses; if the readaddress matches any write address in the set of write addresses, readingdata from an input data path before receiving the read address; and ifthe read address does not match any write address in the set of writeaddresses, reading data from a location in the memory array designatedby the read address.
 34. A method of writing data to an integratedmemory array, following reading data from the integrated memory array,comprising: receiving a first write address in connection with a firstwrite operation; after receiving the write address, receiving a readaddress in connection with a memory read operation; receiving a firstset of write data in connection with the write operation; applying theread address to the memory array in connection with the read operation;storing the first write address in an address register until after theread address is applied to the memory array; storing the first set ofwrite data in a data register until after the read address is applied tothe memory array; and after completion of the read operation, processingthe first write address to store the first set of write data in thememory array.
 35. The method of claim 34 wherein the read operationoccupies N clock cycles and wherein the steps of receiving the writeaddress and receiving the write data are separated by N clock cycles.36. The method of claim 34, further comprising the steps of: beforereceiving the read address, receiving a second write address inconnection with a second write operation; before receiving the readaddress, receiving a second set of write data in connection with thesecond write operation; and after applying the read address to thememory array, processing the second write address to store the secondset of write data in the memory array.
 37. A method of writing to anintegrated memory array, comprising the steps of: temporarily storing awrite address in an interim address register; temporarily storing writedata in an interim data register; monitoring commands to detect anavailable nonreading interval at the memory array; and during thedetected available nonreading interval, transferring the temporarilystored write data from the interim data register to a location in thememory array identified by the temporarily stored write address.
 38. Themethod of claim 37, further comprising the steps of: receiving the writeaddress of the memory device at a first operational interval; andreceiving the write data of the memory device at a second operationalinterval later than the first operational interval.